1. Field of the Invention
The present invention relates to a semiconductor data storing circuit device, a method of checking the semiconductor data storing circuit device and a method of relieving the semiconductor data storing circuit device from a defective cell.
2. Description of Related Art
FIG. 19 is a block diagram showing the configuration of a system LSI in which a plurality of static random access memory (SRAM) cores are arranged. The system LSI denotes an example of a conventional semiconductor data storing circuit device. In FIG. 19, 101 indicates a semiconductor chip, 102 indicates each of a plurality of pads, 103 indicates each of a plurality of memory cores (SRAM cores), 104 indicates each of a plurality of logical circuits, and 105 indicates each of a plurality of selecting circuits. Each selecting circuit 105 selects either one logical circuit 104 or a terminal 202 to be used for a test operation.
FIG. 20 is a block diagram showing the configuration of each memory core 103 shown in FIG. 19. In FIG. 20, 106 indicates a memory cell array having 8xc3x9716 memory cells arranged in 8 rows and 16 columns. 106a indicates each of 128 (8xc3x9716) memory cells (hereinafter, called cells). 106b indicates each of 16 bit lines. 106c indicates each of 8 word lines. 107 indicates a row decoder. 108 indicates each of a plurality of precharge circuits. 109 indicates a column decoder. 110 indicates another column decoder. 111 indicates each of eight multiplexers of one-input (or one-output) and two-output (or two-input). The multiplexer 111 is arranged at every two columns. 112 indicates each of four demultiplexers of one-input and two-output. The demultiplexer 112 is arranged at every four columns. 113 indicates each of four multiplexers of two-input and one-output. The multiplexer 113 is arranged at every four columns. 114 indicates eight sense amplifiers respectively arranged at every two columns. 115 indicates eight write drivers respectively arranged at every two columns. 116 indicates each of four input buffers respectively arranged at every four columns. 117 indicates each of four output buffers respectively arranged at every four columns. D0, D1, D2 and D3 indicate four data input pins. Each data input pin is arranged at every four columns. Q0, Q1, Q2 and Q3 indicate four data output pins. Each data output pin is arranged at every four columns.
Therefore, the memory cell array 106 has a cell configuration of 8 rows and 16 columns. Also, because each bit of the input/output data corresponds to four columns, the memory cell array 106 has a cell configuration of 32 words and 4 bits.
Next, an operation of the memory core 103 will be described below.
A plurality of specific rows are specified by a row address signal input to the row decoder 107, and a plurality of specific columns are specified according to a column address signal input to the column decoders 109 and 110. Thereafter, in a write mode operation, four bits of data input to the corresponding data input pins D0, D1, D2 and D3 are written in four specific cells arranged in the specific rows and the specific columns respectively through the corresponding input buffers 116, the corresponding demultiplexers 112, the corresponding write drivers 115 and the corresponding multiplexers 111. In contrast, in a read mode operation, four bits of data stored in four specific cells of the specific rows and the specific columns are read out as four bits of test data to the corresponding data output pins Q0, Q1, Q2 and Q3 through the corresponding multiplexers 111, the corresponding sense amplifiers 114, the corresponding multiplexers 113 and the corresponding output buffers 117, and the bits of test data are output from the corresponding data output pins Q0, Q1, Q2 and Q3.
FIG. 21 is a block diagram showing the configuration of each memory core 103 in which a checking circuit is arranged. In FIG. 21, 118 indicates each of 4 multiplexers of two-input and one-output. The multiplexer 118 is arranged at every four columns. 119 indicates each of four demultiplexers of one-input and two-output. The demultiplexer 119 is arranged at every four columns. 120 indicates a controller. 121a indicates a column address selector. 121b indicates another column address selector. 122 indicates a row address selector. TD0, TD1, TD2 and TD3 indicate four test data input pins. TQ0, TQ1, TQ2 and TQ3 indicate four test data output pins. The other constituent elements, which are the same as those shown in FIG. 20, are indicated by the same reference numerals as those shown in FIG. 20.
Next, an operation of the memory core 103 shown in FIG. 21 will be described below.
In cases where an operation mode changing signal input to the controller 120 indicates a normal operation mode, each multiplexer 118 is connected with the corresponding data input pin D0, D1, D2 or D3, each of the column address selectors 121a and 121b selects a column address signal, and the row address selector 122 selects a row address signal. Therefore, the same operation as that performed in the memory core 103 shown in FIG. 20 is performed in each of the write and read modes.
In contrast, in cases where an operation mode changing signal input to the controller 120 indicates a test operation mode, each multiplexer 118 is connected with the corresponding test data input pin TD0, TD1, TD2 or TD3, each of the column address selectors 121a and 121b selects a test column address signal, and the row address selector 122 selects a test row address signal.
In this case, a plurality of specific rows are specified according to a test row address signal input to the row decoder 107, and a plurality of specific columns are specified by a test column address signal input to the column decoders 109 and 110. Thereafter, in a write mode operation, four bits of data input to the test data input pins TD0, TD1, TD2 and TD3 are written in four specific cells of the specific rows and the specific columns through the corresponding input buffers 116, the corresponding multiplexers 118, the corresponding demultiplexers 112, the corresponding write drivers 115 and the corresponding multiplexers 111. In contrast, in a read mode operation, four bits of data stored in four specific cells of the specific rows and the specific columns are read out from the corresponding test data output pins TQ0, TQ1, TQ2 and TQ3 through the corresponding multiplexers 111, the corresponding sense amplifiers 114, the corresponding multiplexers 113, the corresponding demultiplexers 119 and the corresponding output buffers 117.
Therefore, in cases where the test operation mode is performed in each memory core 103 shown in FIG. 21, the memory cell array 106 has a cell configuration of 16 columnsxc3x978 rows in the same manner as that in the normal operation mode. Also, because each bit of the input/output test data corresponds to four columns, the memory cell array 106 has a cell configuration of 32 wordsxc3x974 bits. Therefore, an operation check for each memory core 103 is performed according to a checking program applied to a cell configuration of 32 wordsxc3x974 bits in the manufacturing of the system LSI.
Because the semiconductor data storing circuit device (or the system LSI) arranged on a semiconductor chip has the above configuration, in cases where a large number of input/output pins are arranged in the device, a problem has arisen that it is difficult to arrange a plurality of test input/output pins corresponding to the input/output pins.
Also, in cases where a large number of columns correspond to each bit of data input or output in the normal operation mode, another problem has arisen that a test operation time is lengthened so as to increase a manufacturing cost of the device.
Also, in cases where word-bit configurations of the memory cores 103 in the semiconductor data storing circuit device differs from each other, it is required to prepare a checking program for each memory core of the semiconductor data storing circuit device. Therefore, another problem has arisen that the test operation cannot be efficiently performed and the checking cost is increased. In detail, even though all memory cell arrays arranged in one semiconductor data storing circuit device respectively have the same 64-cell configuration of 8 columnsxc3x978 rows, there is a case where the memory cell arrays have a plurality of word-bit configurations such as 16 wordsxc3x974 bits, 32 wordsxc3x972 bits and 64 wordsxc3x971 bit. In this case, a physical position of a cell depends on the word-bit configuration. For example, a position of a defective cell indicated by xe2x80x9c0-th bit and tenth addressxe2x80x9d in FIG. 22A, a position of a defective cell indicated by xe2x80x9c0-th bit and tenth addressxe2x80x9d in FIG. 22B and a position of a defective cell indicated by xe2x80x9c0-th bit and tenth addressxe2x80x9d in FIG. 22C differ from each other. Because the position of a defective cell depends on the word-bit configuration, a checking algorithm corresponding to each word-bit configuration of the memory cell array 106 is required. Also, a method of relieving the memory cell array 106 from a defective cell is required for each word-bit configuration of the memory cell array 106.
Also, in cases where a plurality of memory cores having cell configurations, in which combinations of the numbers of columns and the numbers of rows differ from each other, are arranged in the semiconductor data storing circuit device, it is required to prepare a plurality of checking programs to perform the test operation of the semiconductor data storing circuit device. Therefore, a further problem of increases in ckecking costs has arisen.
Also, in cases where a plurality of types of memory cores are arranged in the semiconductor data storing circuit device and the cell configurations in each type of memory cores differ from each other, a large number of checking programs are required to perform the test operation for the types of memory cores of the semiconductor data storing circuit device. Therefore, a yet further problem of increases in ckecking costs has arisen.
Also, because the semiconductor data storing circuit device has the above configuration shown in FIG. 20 and FIG. 21, in cases where a spare memory cell array is additionally arranged in a memory core to relieve a memory cell array of the memory core from a defective cell of the memory cell array, another problem has arisen that a test operation of the spare memory cell array cannot be performed in advance before the relief of the memory cell array.
Also, in cases where a failure occurs in a cell of a memory cell array due to an operation speed of the memory cell array, another problem has arisen that there is no guarantee that the memory cell array is relieved from a defective cell by using a spare memory cell array.
Also, in cases where a plurality of memory cell arrays having cell configurations different from each other are arranged in a memory core of the semiconductor data storing circuit device, the number of rows and the number of columns in each memory cell array differ from those in the other memory cell arrays. In this case, when a plurality of spare memory cell arrays are arranged in the memory core to relieve a specific memory cell array from a defective cell of the specific memory cell array arranged in the memory core, another problem has arisen that the processing from the operation check of the memory cell arrays and the spare memory cell arrays to the relief of each memory cell array is complicated and the semiconductor data storing circuit device cannot be efficiently manufactured.
A main object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor data storing circuit device, a semiconductor data storing circuit device and a method of checking the device in which the number of test data input/output pins (or lines) required for a test operation of a memory cell array in the manufacturing of the memory cell array is reduced.
Also, a first subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of checking the device in which the duration of a test operation required for a test operation of a memory cell array in the manufacturing of the memory cell array is shortened.
Also, a second subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of checking the device in which a test operation of a plurality of memory cell arrays is performed according to one checking program even though word-bit configurations of the memory cell arrays differ from each other.
Also, a third subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of checking the device in which a test operation is performed for a plurality of memory cell arrays arranged in a chip according to one checking program even though a combination of the number of rows and the number of columns in each memory cell array differs from those in the other memory cell arrays.
Also, a fourth subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of checking the device in which a test operation is performed for a plurality of memory cell arrays of each type of memory core according to one checking program in cases where a plurality of types of memory cores are arranged in a semiconductor chip and combinations of the numbers of rows and the numbers of columns of the memory cell arrays in each type of memory cores differ from each other.
Also, a fifth subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of relieving the device from a defective memory cell in which a memory cell array of a memory core is efficiently relieved from a defective memory cell existing in the memory cell array even though a spare memory cell array is arranged in the memory core.
Also, a sixth subordinate object of the present invention is to provide a semiconductor data storing circuit device and a method of relieving the device from a defective memory cell in which the processing from a test operation for a plurality of memory cell arrays placed on a semiconductor chip to the relief of each memory cell array from a defective memory cell existing in the memory cell array is efficiently performed by using a plurality of spare memory cell arrays placed with the memory cell arrays in the semiconductor chip even though a combination of the number of rows and the number of columns in each memory cell array differs from those in the other memory cell arrays.
The main object or the first subordinate object is achieved by the provision of a semiconductor data storing circuit device, comprising a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, a data input/output circuit which is arranged in the memory core to be used in a normal operation of the memory cell array and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, and a checking circuit which is arranged in the memory core to be used in a test operation performed in manufacturing of the memory cell array and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array on condition that the second predetermined number of columns differs from the first predetermined number of columns.
Accordingly, the number of test data input/output lines can be reduced in cases where the second predetermined number of columns is higher than the first predetermined number of columns, and a time required for the test operation in the manufacturing of the memory cell array can be shortened in cases where the second predetermined number of columns is lower than the first predetermined number of columns.
It is preferred that the second predetermined number of columns corresponding to the test data input line or/and the test data output line of the checking circuit is higher than the first predetermined number of columns corresponding to the data input line or/and the data output line of the data input/output circuit.
Accordingly, the number of test data input/output lines can be reduced.
It is preferred that the second predetermined number of columns corresponding to the test data input line or/and the test data output line of the checking circuit is lower than the first predetermined number of columns corresponding to the data input line or/and the data output line of the data input/output circuit.
Accordingly, because the number of memory cells simultaneously checked is increased, a time required for the test operation in the manufacturing of the memory cell array can be shortened.
The second, third or fourth subordinate object is achieved by the provision of a semiconductor data storing circuit device, which has a plurality of memory cores on a semiconductor chip, comprising a memory cell array which is arranged in each memory core and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, a data input/output circuit which is arranged in each memory core to be used in a normal operation of the memory cell array of the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at columns defined by an arbitrary number of the memory cell array, and a checking circuit which is arranged in each memory core to be used in a test operation performed in manufacturing of the memory cell array of the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every predetermined number of columns of the memory cell array on condition that the predetermined number of columns is common to the memory cores regardless of the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of the memory core.
Accordingly, the test operation can be performed by using one checking program.
It is preferred that the number of rows and the number of columns in the memory cell array of each memory core are the same as those in the memory cell arrays of the other memory cores, and the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of each memory core differs from the arbitrary number of columns in the data input/output circuits of the other memory cores.
Accordingly, even though a bit-word configuration of the memory cell array in one memory core differs from those in the other memory cores in cases where combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the memory cores are the same as each other, the test operation for the memory cell arrays can be performed by using one checking program.
It is preferred that a combination of the number of rows and the number of columns in the memory cell array of each memory core differs from combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the other memory cores.
Accordingly, the test operation for the memory cores can be performed by using one checking program by adding a virtual memory cell array to each memory cell array to make all memory cell arrays have the same column number and the same row number.
It is preferred that the memory cores are classified into a plurality of types of memory cores, a combination of the number of rows and the number of columns in the memory cell array of each memory core of one type differs from combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the other memory cores of the type for each type of memory cores, the data input line or/and the data output line for each bit of data is/are arranged at every arbitrary number of columns of the memory cell array in each data input/output circuit of one type of memory cores for each type of memory cores, and the test data input line or/and the test data output line for each bit of test data is/are arranged in each checking circuit of one type of memory cores every predetermined number of columns of the memory cell array for each type of memory cores on condition that the predetermined number of columns is common to one type of the memory cores regardless of the arbitrary number of columns in the corresponding data input/output circuit for each type of memory cores.
Accordingly, in cases where a virtual memory cell array is added to each memory cell array to make all memory cell arrays have the maximum column number and the maximum row number for each type of memory cores, the test operation for the memory cores can be performed by using one checking program for each type of memory cores.
The fifth subordinate object is achieved by the provision of a semiconductor data storing circuit device, comprising, a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, a data input/output circuit which is arranged in the memory core to be used in a normal operation of the memory cell array and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, a checking circuit which is arranged in the memory core to be used in a test operation performed in manufacturing of the memory cell array and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array, a spare memory cell array which is arranged in the memory core to relieve the memory cell array from a defective memory cell placed at an arbitrary column of the memory cell array and in which the number of columns is equal to the number of columns corresponding to each bit of test data in the checking circuit, and a change-over circuit for changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns corresponding to each bit of data in the data input/output circuit, to a block of columns of the spare memory cell array.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell.
The fifth subordinate object is achieved by the provision of a semiconductor data storing circuit device, comprising a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, a data input/output circuit which is arranged in the memory core to be used in a normal operation of the memory cell array and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, a checking circuit which is arranged in the memory core to be used in a test operation performed in manufacturing of the memory cell array and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array, a spare memory cell array which is arranged in the memory core to relieve the memory cell array from a defective memory cell placed at an arbitrary column of the memory cell array and in which the number of columns is equal to the number of columns corresponding to each bit of test data in the checking circuit, a plurality of first change-over circuits, which are directly connected with the memory cell array, for respectively changing over from one column of the memory cell array to another column of the memory cell array in the normal operation, and a second change-over circuit for changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns processed in each first change-over circuit, to a block of columns of the spare memory cell array.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell. In addition, because the number of blocks of columns of the spare memory cell array is high as compared with that in the changing of each block of columns of the memory cell array of which the column number is equal to the number of columns corresponding to one bit of data in the data input/output circuit, the memory cell array can be efficiently relieved from the defective memory cell.
The fifth subordinate object is achieved by the provision of a semiconductor data storing circuit device, comprising a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, a data input/output circuit which is arranged in the memory core to be used in a normal operation of the memory cell array and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, a checking circuit which is arranged in the memory core to be used in a test operation performed in manufacturing of the memory cell array and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array on condition that the second predetermined number of columns is lower than the first predetermined number of columns, a spare memory cell array which is arranged in the memory core to relieve the memory cell array from a defective memory cell placed at an arbitrary column of the memory cell array and in which the number of columns is equal to N times (N is a positive integral number) of the number of columns corresponding to each bit of test data in the checking circuit, and a change-over circuit for changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns corresponding to each bit of data in the checking circuit, to a block of columns of the spare memory cell array.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell.
The sixth subordinate object is achieved by the provision of a semiconductor data storing circuit device, which has a plurality of memory cores on a semiconductor chip, comprising a memory cell array which is arranged in each memory core and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns on condition that a combination of the number of rows and the number of columns in the memory cell array of each memory core differs from those in the memory cell arrays of the other memory cores, a data input/output circuit which is arranged in each memory core to be used in a normal operation of the memory cell array of the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every arbitrary number of columns of the memory cell array, a checking circuit which is arranged in each memory core to be used in a test operation performed in manufacturing of the memory cell array of the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every predetermined number of columns of the memory cell array on condition that the predetermined number of columns is common to the memory cores regardless of the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of the memory core, and a spare memory cell array which is arranged in each memory core to relieve the memory cell array of the memory core from a defective memory cell placed at an arbitrary column of the memory cell array and in which the number of columns is equal to N times (N is a positive integral number) of the number of columns corresponding to each bit of test data in the checking circuit.
Accordingly, even though a plurality of memory cell arrays having combinations of the numbers of columns, the numbers of rows, the numbers of bits and the numbers of words different from each other are arranged in the same semiconductor chip, the processing from the test operation for the memory cell arrays to the relief of each memory cell array from a defective memory cell existing in the memory cell array can be performed according to one checking program having one algorithm.
The main object or the first subordinate object is achieved by the provision of a method of checking a semiconductor data storing circuit device, comprising the steps of preparing a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, preparing a data input/output circuit which is arranged in the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, preparing a checking circuit which is arranged in the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array on condition that the second predetermined number of columns differs from the first predetermined number of columns, and performing a test operation for the memory cell array through the test data input lines or/and the test data output lines of the checking circuit to perform a normal operation for the memory cell array through the data input lines or/and the data output lines of the data input/output circuit.
Accordingly, the number of test data input/output lines can be reduced in cases where the second predetermined number of columns is higher than the first predetermined number of columns, and a time required for the test operation in the manufacturing of the memory cell array can be shortened in cases where the second predetermined number of columns is lower than the first predetermined number of columns.
It is preferred that the second predetermined number of columns corresponding to the test data input line or/and the test data output line of the checking circuit is higher than the first predetermined number of columns corresponding to the data input line or/and the data output line of the data input/output circuit.
Accordingly, the number of test data input/output lines can be reduced.
It is preferred that the second predetermined number of columns corresponding to the test data input line or/and the test data output line of the checking circuit is lower than the first predetermined number of columns corresponding to the data input line or/and the data output line of the data input/output circuit.
Accordingly, because the number of memory cells simultaneously checked is increased, a time required for the test operation in the manufacturing of the memory cell array can be shortened.
The second, third or fourth subordinate object is achieved by the provision of a method of checking a semiconductor data storing circuit device, comprising the steps of preparing a memory cell array which is arranged in each of a plurality of memory cores of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, preparing a data input/output circuit which is arranged in each memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every arbitrary number of columns of the memory cell array of the memory cell, preparing a checking circuit which is arranged in each memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every predetermined number of columns of the memory cell array on condition that the predetermined number of columns is common to the memory cores regardless of the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of the memory core, and performing a test operation for the memory cell array of each memory core through the test data input lines or/and the test data output lines of the checking circuit of the memory core to perform a normal operation for the memory cell array of the memory core through the data input lines or/and the data output lines of the data input/output circuit of the memory core.
Accordingly, the test operation can be performed by using one checking program.
It is preferred that the number of rows and the number of columns in the memory cell array of each memory core are the same as those in the memory cell arrays of the other memory cores, and the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of each memory core differs from the arbitrary number of columns in the data input/output circuits of the other memory cores.
Accordingly, even though a bit-word configuration of the memory cell array in one memory core differs from those in the other memory cores in cases where combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the memory cores are the same as each other, the test operation for the memory cell arrays can be performed by using one checking program.
It is preferred that a combination of the number of rows and the number of columns in the memory cell array of each memory core differs from combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the other memory cores.
Accordingly, the test operation for the memory cores can be performed by using one checking program by adding a virtual memory cell array to each memory cell array to make all memory cell arrays have the same column number and the same row number.
The second, third or fourth subordinate object is achieved by the provision of a method of checking a semiconductor data storing circuit device, comprising the steps of:
classifying a plurality of memory cores of a semiconductor chip into a plurality of types of memory cores;
preparing a memory cell array which is arranged in each memory core and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns on condition that a combination of the number of rows and the number of columns in the memory cell array of each memory core of one type differs from combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the other memory cores of the type for each type of memory cores;
preparing a data input/output circuit which is arranged in each memory core of one type and in which a data input line or/and a data output line for each bit of data is/are arranged at every arbitrary number of columns of the memory cell array of the memory cell for each type of memory cores;
preparing a checking circuit which is arranged in each memory core of one type and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every predetermined number of columns of the memory cell array for each type of memory cores on condition that the predetermined number of columns is common to the memory cores regardless of the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of the memory core on condition that the predetermined number of columns is common to one type of the memory cores regardless of the arbitrary number of columns in the corresponding data input/output circuit for each type of memory cores; and
performing a test operation for the memory cell array of each memory core through the test data input lines or/and the test data output lines of the checking circuit of the memory core to perform a normal operation for the memory cell array of the memory core through the data input lines or/and the data output lines of the data input/output circuit of the memory core.
Accordingly, in cases where a virtual memory cell array is added to each memory cell array to make all memory cell arrays have the maximum column number and the maximum row number for each type of memory cores, the test operation for the memory cores can be performed by using one checking program for each type of memory cores.
The fifth subordinate object is achieved by the provision of a method of relieving the semiconductor data storing circuit device from a defective memory cell, comprising the steps of preparing a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, preparing a data input/output circuit which is arranged in the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, preparing a checking circuit which is arranged in the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array, preparing a spare memory cell array which is arranged in the memory core and in which the number of columns is equal to the number of columns corresponding to each bit of test data in the checking circuit, performing a test operation for the memory cell array of each memory core through the test data input lines or/and the test data output lines of the checking circuit of the memory core to detect a defective memory cell placed at an arbitrary column of one memory cell array, and changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns corresponding to each bit of data in the data input/output circuit, to a block of columns of the spare memory cell array to relieve the memory cell array from the defective memory cell in cases where the defective memory cell placed at the block of columns of the memory cell array is detected according to the test operation.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell.
The fifth subordinate object is achieved by the provision of a method of relieving the semiconductor data storing circuit device from a defective memory cell, comprising the steps of preparing a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, preparing a data input/output circuit which is arranged in the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, preparing a checking circuit which is arranged in the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array, preparing a spare memory cell array which is arranged in the memory core and in which the number of columns is equal to the number of columns corresponding to each bit of test data in the checking circuit, preparing a plurality of first change-over circuits, which are directly connected with the memory cell array, for respectively changing over from one column of the memory cell array to another column of the memory cell array, performing a test operation for the memory cell array through the test data input lines or/and the test data output lines of the checking circuit to detect a defective memory cell placed at an arbitrary column of the memory cell array, and changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns processed in each first change-over circuit, to a block of columns of the spare memory cell array to relieve the memory cell array from the defective memory cell in cases where the defective memory cell placed at the block of columns of the memory cell array is detected according to the test operation.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell. In addition, because the number of blocks of columns of the spare memory cell array is high as compared with that in the changing of each block of columns of the memory cell array of which the column number is equal to the number of columns corresponding to one bit of data in the data input/output circuit, the memory cell array can be efficiently relieved from the defective memory cell.
The fifth subordinate object is achieved by the provision of a method of relieving the semiconductor data storing circuit device from a defective memory cell, comprising the steps of preparing a memory cell array which is arranged in a memory core of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns, preparing a data input/output circuit which is arranged in the memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every first predetermined number of columns of the memory cell array, preparing a checking circuit which is arranged in the memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every second predetermined number of columns of the memory cell array on condition that the second predetermined number of columns is lower than the first predetermined number of columns, preparing a spare memory cell array which is arranged in the memory core and in which the number of columns is equal to N times (N is a positive integral number) of the number of columns corresponding to each bit of test data in the checking circuit, performing a test operation for the memory cell array through the test data input lines or/and the test data output lines of the checking circuit to detect a defective memory cell placed at an arbitrary column of the memory cell array, and changing a block of columns of the memory cell array, which includes a defective memory cell and of which the column number is equal to the number of columns corresponding to each bit of data in the checking circuit, to a block of columns of the spare memory cell array to relieve the memory cell array from the defective memory cell in cases where the defective memory cell placed at the block of columns of the memory cell array is detected according to the test operation.
Accordingly, the test operation can be performed without distinguishing the spare memory cell array from the memory cell array, and the memory cell array can be relieved from the defective memory cell by using the spare memory cell array. Also, the test operation can be performed before the relief of the memory cell array from the defective memory cell.
The sixth subordinate object is achieved by the provision of a method of relieving the semiconductor data storing circuit device from a defective memory cell, comprising the steps of preparing a memory cell array which is arranged in each of a plurality of memory cores of a semiconductor chip and has a plurality of memory cells arranged in a row or a plurality of rows and a plurality of columns on condition that a combination of the number of rows and the number of columns in the memory cell array of each memory core differs from combinations of the numbers of rows and the numbers of columns in the memory cell arrays of the other memory cores, preparing a data input/output circuit which is arranged in each memory core and in which a data input line or/and a data output line for each bit of data is/are arranged at every arbitrary number of columns of the memory cell array of the memory cell, preparing a checking circuit which is arranged in each memory core and in which a test data input line or/and a test data output line for each bit of test data is/are arranged at every predetermined number of columns of the memory cell array on condition that the predetermined number of columns is common to the memory cores regardless of the arbitrary number of columns corresponding to the data input line or/and the data output line for each bit of data in the data input/output circuit of the memory core, preparing a spare memory cell array which is arranged in each memory core and in which the number of columns is equal to N times (N is a positive integral number) of the number of columns corresponding to each bit of test data in the checking circuit, and relieving the memory cell array of a specific memory core from a defective memory cell by using the spare memory cell array in cases where the defective memory cell exists in the memory cell array of the specific memory core.
Accordingly, even though a plurality of memory cell arrays having combinations of the numbers of columns, the numbers of rows, the numbers of bits and the numbers of words different from each other are arranged in the same semiconductor chip, the processing from the test operation for the memory cell arrays to the relief of each memory cell array from a defective memory cell existing in the memory cell array can be performed according to one checking program having one algorithm.